1. Field of Invention
The present invention generally relates to a layout structure and method, more particularly, to a layout structure and method for supporting central processing units having two different package techniques.
2. Description of Related Art
The Pentium IV central processing unit (abbreviated as CPU) developed by Intel Corporation has two different package types: one type of CPU has 423 pins and uses the pin grid array (abbreviated as PGA) package; the other type of CPU has 478 pins and uses the ball grid array (abbreviated as BGA) package. Since these two different package techniques are configured on a motherboard that has 6 layers and 4 layers stack structure respectively, it needs to use a layout structure of different printed circuit boards and has to cooperate with different north bridge control chips to work properly. Therefore, it is not only inconvenient in usage, but also the manufacture cost is increased.
The conventional stack structure of the printed circuit board of the 423 pins Pentium IV CPU is shown in Table 1:
TABLE 1Top Signal LayerGrounded LayerInner Signal LayerGrounded LayerPower LayerBottom Solder Layer
From Table 1, the printed circuit board uses a 6 layers stack structure. From up to down, the stack structure sequentially comprises a top signal layer, a grounded layer, an inner signal layer, a grounded layer, a power layer, and a bottom solder layer. FIG. 1 schematically shows a power layer cut ichnography in the area where the signals of the north bridge control chip 102 are coupled to the signals of the CPU 100 in the layout structure of a motherboard that supports the 423 pins Pentium IV CPU. From Table 1, since all the signals of the north bridge control chip 102 that are coupled to the CPU 100 are placed on the top signal layer and the grounded layer, all the signals of the north bridge control chip 102 that are coupled to the CPU 100 can refer to the grounded layer. Therefore, high quality of the signal transmission can be assured. On the other hand, from the layout structure of Table 1 and FIG. 1, since the power layer 104 of the north bridge control chip 102 that is coupled to the CPU 100 does not comprise a grounded potential, if the signals of the north bridge control chip 102 that are coupled to the CPU 100 are to be placed on the bottom solder layer, it has to cross over the power layer 104 to refer to the grounded area, thus the signal transmission quality is not as good as in the top signal layer. Consequently, the conventional bottom solder layer is seldom used to place the signals of the north bridge control chip that are coupled to the CPU.
On the other hand, the stack structure of the conventional printed circuit board that supports the 478 pins Pentium IV CPU is shown in Table 2:
TABLE 2The area of the north bridgeThe area of the north bridgeCPUcontrol chip where itscontrol chip where its(The first area)signals are not coupled tosignals are coupled to thethe CPU (The third area)CPU (The second area)Top Signal LayerTop Signal LayerTop SignalLayerGNDGNDGNDThe Cut Layer of theGNDGNDinterface operating voltagesourceBottom Solder LayerBottom Solder LayerBottomSolder Layer
From Table 2, the printed circuit board uses a 4 layers stack structure, comprising: a first area, where the whole CPU is placed in the first area; a second area, all the signals of the north bridge control chip that are coupled to the CPU are placed in the second area; a third area, all the signals of the north bridge control chip that are not coupled to the CPU are placed in the third area. From Table 2, the stack structure of the first area from up to down sequentially comprises a top signal layer, a grounded layer (GND), a power layer having an interface operating voltage source (to generate a voltage source via the appropriate cutting, and each interface voltage source varies based on the difference of the connected devices), and a bottom solder layer. The stack structure of the second area and third area from up to down sequentially comprises a top signal layer, a grounded layer, a grounded layer, and a bottom solder layer. All the signals of the Intel designed north bridge control chip that are connected to the CPU are placed on the top signal layer, and all refer to the contiguous grounded layer. However, since most of the signals are placed on the top signal layer, thus the area used by the north bridge control chip is increased, and greater printed circuit board is demanded to constitute the control chip, moreover the area of the north bridge control chip that is coupled to the CPU is also increased accordingly, so that the demand of the layout length can be met. These limitations cause great concern in designing the north bridge control chip and the motherboard.
Obviously, since the stack structure of these two Intel Pentium IV CPUs mentioned above are different, the prior art has to use two different layout structures and printed circuit boards to support two different Intel Pentium IV CPUs that have different package types. As a result, Intel has been forced to develop two different types of the north bridge control chip to support the corresponding Pentium IV CPU respectively. Consequently, in order to support the Intel Pentium IV CPUs of two different package types, not only does the motherboard need to be relaid out, but the north bridge control chip also needs to be replaced. This results in usage inconveniency and cost increase.